1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device and methods of manufacturing the same, and more particularly, to a phase-change semiconductor memory device and methods of manufacturing the same.
2. Description of the Related Art
Semiconductor devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, etc. may be included in various electric and/or electronic apparatuses. Semiconductor devices may generally be classified as volatile memory devices or nonvolatile memory devices. Volatile memory devices may lose data stored therein when a power supply is turned off or drops below a voltage threshold, whereas nonvolatile memory devices may maintain data stored therein even after a power supply is turned off or drops below a voltage threshold. In an example, nonvolatile memory devices such as flash memory devices may be employed within digital cameras, MP3 players, cellular phones, etc., to maintain data integrity without a constant power supply.
Conventional flash memory devices may have longer read access and programming times as compared to random access memory (RAM) devices. A ferroelectric random access memory (FRAM) device, a magnetic random access memory (MRAM) device, a phase-change random access memory (PRAM) device, etc. may be employed which may have faster read access and programming times than flash memory devices.
Conventional PRAM devices may include a phase-change material which may alternate between a crystalline structure and an amorphous structure in accordance with heat generated by electrical power or current. An example of conventional phase-change materials which may be included in a PRAM device may include a chalcogenide alloy. The chalcogenide alloy may include a mixture of germanium (Ge), antimony (Sb) and tellurium (Te), and may be referred to as a “GST”.
Conventional PRAM devices may include a phase-change layer configured to receive an electric current. A crystalline phase of the phase-change material may be adjusted based on a current level and a duration of the received electric current. Conventional PRAM devices may have a resistance which may vary based on a phase of the phase-change material, such that the crystalline and amorphous phases are each associated with different resistances. For example, the phase-change material in the crystalline phase may have a lower resistance than the phase-change material in the amorphous phase. The difference in the resistances of the crystalline and amorphous phases of the phase-change material may allow the PRAM device to be associated with one of a first logic level (e.g., a higher logic level) and a second logic level (e.g., a lower logic level). Examples of PRAM devices are well known in the art.
FIG. 1 is a cross-sectional view illustrating a phase change memory cell of a conventional PRAM device.
Referring to FIG. 1, the PRAM device may include a semiconductor substrate 10, an insulating interlayer pattern 11 formed on the semiconductor substrate 10, a contact plug 14 formed within the insulating interlayer pattern 11, a first insulation layer pattern 20a formed on the insulating interlayer pattern 11, a metal layer pattern 30a formed within the first insulation layer pattern 20a, a second insulation layer pattern 34b formed on the first insulation layer pattern 20a, a contact electrode 40a formed within the second insulation layer pattern 34b, a phase-change layer pattern 44a formed on the second insulation layer pattern 34b, an upper electrode 48a formed on the phase-change layer pattern 44a and a third insulation layer pattern 52a formed on the upper electrode 48a. 
Referring to FIG. 1, the contact plug 14 may contact an impurity region (not shown) of the semiconductor substrate 10. The metal layer pattern 30a may contact the contact plug 14. The metal layer pattern 30a may electrically connect the contact electrode 40a to the contact plug 14. A spacer S may be formed within the second insulation layer pattern 34b to surround the contact electrode 40a. 
Referring to FIG. 1, the metal layer pattern 30a may be formed by a damascene process such that a void V or a seam may be generated in the metal layer pattern 30a. The void V may be generated below the contact electrode 40a and/or the phase-change layer pattern 44a and may be characterized by a higher electrical resistance than other portions of the metal layer pattern 30a. The void V may at least partially isolate the contact electrode 40a from the metal layer pattern 30a. 
Referring to FIG. 1, the metal layer pattern 30a may alternatively be formed by a dry etching process. In conventional dry etching processes, a hard mask pattern (not shown) may be formed on the metal layer 30a. The metal layer 30a may be dry-etched using the hard mask pattern as an etching mask. The dry etching process may reduce an occurrence of the void V in conventional PRAM devices.
Referring to FIG. 1, while the dry etching process may reduce an occurrence of voids, various problems may be associated with the above-described dry etching process. For example, the hard mask pattern (not shown) may remain on the metal layer pattern 30a with a thickness greater than about 3,000 Å after the dry etching process. Thus, if the contact electrode 40a is formed through the hard mask pattern and the second insulation layer pattern 34b, the contact electrode 40a may not be formed with a desired resistance. The hard mask pattern and the second insulation layer pattern 34b, which may have uniform thicknesses, may thereby not be formed. The contact electrode 40a may not be uniformly formed at a given height through the hard mask pattern and the second insulation layer pattern 34b. Furthermore, a contact hole for forming the contact electrode 40a may not be formed through the hard mask pattern and the second insulation layer pattern 34b with higher levels of accuracy. The spacer S may also not be formed through the hard mask pattern and the second insulation layer pattern 34b. Accordingly, it may be more difficult to control an electrical current through the contact electrode 40a, which may degrade an operational performance of conventional PRAM devices.